1. Field of the Invention
The invention relates to the field of CMOS processes and fabrication techniques.
2. Prior Art
Complementary metal-oxide-semiconductor (CMOS) transistors also known as COS/MOS transistors are well known in the art and are often employed in applications requiring low power consumption. For example, such devices because of their low "standby" power consumption are used for battery operated wrist-watches, hand-held calculators, and the like. Moreover, CMOS field-effect transistors are characterized by their high switching speeds and their very high noise immunity over a wide range of power supply voltages.
In high voltage LSI CMOS devices, channel stops (also referred to as "guard bands") are used in the substrate, surrounding each of the active devices. Channel stops are typically highly doped "frames" of the same conductivity type as the host region for the active device. They are used to reduce leakage between neighboring device such as that caused by spurious MOS action. This MOS action often results from potentials on interconnecting lines, and the like.
High voltage LSI CMOS devices not employing channel stops, often use thick field oxides and heavily doped substrates and wells to reduce parasitic MOS action. These devices have high threshold voltages, high capacitance, high body-effect, and thus, poor AC performance. Wide diffusion spacing is required resulting in low density circuits. Moreover, masking becomes more difficult on the uneven surfaces caused by the thick field oxides.
In other CMOS circuits moderately thick oxides are employed with full channel stops (that is, an n-type channel stop surrounding the n-channel device and a p-type channel stop surrounding the p-type device). Full channel stops are most often spaced-apart from the active devices which they surround since they are heavily doped (diffused) regions which would otherwise provide low breakdown voltage junctions when contiguous with the source and drain regions. An example of this structure is shown in FET Principles, Experiments, and Projects by Edward M. Noll published by Howard W. Sams & Company, Inc. and the Bobbs-Merrill Company, Inc. (second edition) at page 241, FIG. 8-3. These circuits are of lower density.
Another technique for providing channel stops through use of an ion implanted surface layer is described in "Surface Doping Using Ion Implantation For Optimum Guard Layer Design In COS/MOS Structures" by Douglas and Dingwall, IEEE Transactions on Electron Devices (Vol. ED22), October 1975, beginning at page 849. As may be seen in FIG. 3 the n-channel stop and p-channel stop are spaced apart, thus decreasing device density.
In one commonly employed process for fabricating CMOS devices, a well (such as a p-well) is first formed with a masking operation. Then, with another masking operation, the n-channel device is fabricated in the p-well along with the formation of the n-channel stop. Following this, additional masking is required to define and form the p-channel device and p-channel stop. The channel stops, of necessity, must be spaced apart from the active device.
With the disclosed process channel stops are fabricated in alignment with each other, and in alignment with the active devices, without extra masking steps. Moreover, the channel stops are contiguous with each other and with the source and drain regions of the active devices, permitting high density fabrication. The resultant structure is relatively flat, that is, very thick field oxides are not required and the necessary field oxides are recessed into the silicon substrate.
The invented process employs, in part, local oxidation of silicon (LOCOS) techniques. For a general discussion of this technology, see Semiconductor Silicon edited by Huff & Burgess, Princeton, N.J., 1973, page 860 under the title "Selective Oxidation of Silicon and its Device Application" by Kooi & Appels; "Invited:MOS Effects and Silicon Device Technology" by Kooi, Proceedings of the 5th Conference (1973 International) on Solid State Devices, Tokoyo, 1973, page 427; and, "Local Oxidation of Silicon/CMOS Technology/Design System for LSI in CMOS", IEEF International Solid State Circuit Conference (Digest of Technical Papers) Session VI:LSI Logic, 1974, beginning on page 60.